Signal Tabl es
374 October 8, 2006
Preliminary
PWM4 35 O TTL P ulse width modulator channel 4 output.
PWM5 36 O TTL P ulse width modulator channel 5 output.
SSI SSIClk 1 9 I/O TTL SSI clock reference (input when in slave
mode and output in master mode).
SSIFss 20 I/O TTL SSI frame enable (input for an SSI slave
device and output for an SSI master device).
SSIRx 21 I TTL SSI receive data input.
SSITx 22 O TTL SSI transmit data output.
System Control &
Clocks
OSC0 9 I Analog Oscillator crystal input or an external clock
reference input.
OSC1 10 O Analog Oscillator crystal output.
RST
5 I TTL System reset input.
UART U0Rx 17 I TTL UART0 receive data input.
U0Tx 18 O TTL UART0 transmit data output.
U1Rx 27 I TTL UART1 receive data input.
U1Tx 28 O TTL UART1 transmit data output.
Table 17-4. GPIO Pins and Alternate Functions (Sheet 1 of 2)
GPIO Pin
Pin
Number
Multiplexed
Function
Multiplexed
Function
PA0 17 U0Rx
PA1 18 U0Tx
PA2 19 SSIClk
PA3 20 SSIFss
PA4 21 SSIRx
PA5 22 SSITx
PB0 29 PWM2
PB1 30 PWM3
PB2 33 I2CSCL
PB3 34 I2CSDA
PB4 44
PB5 43 CCP5
Table 17-3. Signals by Function, Except for GPIO (Sheet 3 of 3)
Function Pin Name
Pin
Number
Pin
Type
Buffer
Type
Description
