Signal Tabl es
372 October 8, 2006
Preliminary
SSIFss 20 I/O TTL SSI frame enable (input for an SSI slave device and output for an
SSI ma ste r device).
SSIRx 21 I TTL SSI receive data input.
SSITx 22 O TTL SSI transmit data output.
SWCLK 40 I TTL Serial wire clock reference input.
SWDIO 39 I/O TTL Serial-wire debug inp ut/o utp ut.
SWO 37 O TTL Serial-wire output.
TCK 40 I TTL JTAG scan test clock reference input.
TDI 38 I TTL JTAG scan test data input.
TDO 37 O TTL JTAG scan test data output.
TMS 3 9 I TTL JTAG scan te st mode select input.
TRST
41 I TTL JTAG scan test rese t input.
U0Rx 17 I TTL UART0 receive data input.
U0Tx 18 O TTL UART0 transmit data output.
U1Rx 27 I TTL UART1 receive data input.
U1Tx 28 O TTL UART1 transmit data output.
VDD 7 - Power Positive supply for logic and I/O pins.
VDD 15 - Power Positive supply for logic and I/O pins.
VDD 23 - Power Positive supply for logic and I/O pins.
VDD 32 - Power Positive supply for logic and I/O pins.
Table 17-3. Signals by Function, Except for GPIO (Sheet 1 of 3)
Function Pin Name
Pin
Number
Pin
Type
Buffer
Type
Description
ADC ADC0 1 I Analog Analog-to-digital converte r input 0.
ADC1 2 I Analog Analog-to-digital converter input 1.
General-Purpose
Timers
CCP0 45 I/O TTL Timer 0 capture input, compare output, or
PWM output channel 0.
CCP1 3 I/O TTL Timer 0 capture input, compare output, or
PWM output channel 1.
CCP2 46 I/O TTL Timer 1 capture input, compare output, or
PWM output channel 2.
Table 17-2. Signals by Signal Name (Sheet 3 of 3)
Pin Name
Pin
Number
Pin
Type
Buffer
Type
Description