LM3S610 Data Sheet
October 8, 2006 369
Preliminary
34 PB3 I/O TTL GPIO port B bit 3.
I2CSDA I/O OD I
2
C ser ial da ta.
35 PE0 I/O TTL GPIO port E bit 0.
PWM4 O TTL Pulse width modulator channel 4 output.
36 PE1 I/O TTL GPIO port E bit 1.
PWM5 O TTL Pulse width modulator channel 5 output.
37 PC3 I/O TTL GPIO port C bit 3.
TDO O TTL JTAG scan test data output.
SWO O TTL Serial-wire output.
38 PC2 I/O TTL GPIO port C bit 2.
TDI I TTL JTAG scan test data input.
39 PC1 I/O TTL GPIO port C bit 1.
TMS I TTL JTAG sca n test mode select input.
SWDIO I/O TTL Serial-wire debug inp ut/o utp ut.
40 PC0 I/O TTL GPIO port C bit 0.
TCK I TTL JTAG scan test clock reference input.
SWCLK I TTL Serial wire clock reference input.
41 PB7 I/O TTL GPIO port B bit 7.
TRST
I TTL JTAG scan test re set input.
42 PB6 I/O TTL GPIO port B bit 6.
43 PB5 I/O TTL GPIO port B bit 5.
CCP5 I/O TTL Timer 2 capture input, compare output, or PWM output channel 5.
44 PB4 I/O TTL GPIO port B bit 4.
45 PD4 I/O TTL GPIO port D bit 4.
CCP0 I/O TTL Timer 0 capture input, compare output, or PWM output channel 0.
46 PD5 I/O TTL GPIO port D bit 5.
CCP2 I/O TTL Timer 1 capture input, compare output, or PWM output channel 2.
47 PD6 I/O TTL GPIO port D bit 6.
Fault I TTL PWM fault detect input.
48 PD7 I/O TTL GPIO port D bit 7.
Table 17-1. Signals by Pin Number (Sheet 3 of 3)
Pin
Number
Pin Name
Pin
Type
Buffer
Type
Description