LM3S610 Data Sheet
October 8, 2006 365
Preliminary
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this
register is ignored. If the value of this register is larger than the width of a Low pulse on the input
PWM signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low
time on the output. Care must be taken to ensure that the input Low time always exceeds the
falling-edge delay . In a similar manner , PWM3 is generated from PWM1A with its falling edge delayed
and PWM5 is produced from PWM2A with its falling edge delayed.
Bit/Field Name Type Reset Description
31:12 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
11:0 FallDelay R/W 0 The number of clock ticks to delay the falling edge.
reserved
RO
0
PWMn Dead-Band Falling-Edge-Delay Register (PWMnDBFALL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
FallDelay
