Pulse Width Modulator (PWM)
364 October 8, 2006
Preliminary
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the
PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge
delayed.
Bit/Field Name Type Reset Description
31:12 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
11:0 RiseDelay R/W 0 The number of clock ticks to delay the rising edge.
reserved
RO
0
PWMn Dead-Band Rising-Edge Delay (PWMnDBRISE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
RiseDelay
