Pulse Width Modulator (PWM)
358 October 8, 2006
Preliminary
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8
These registers contain a value to be compared against the counter (PWM0CMPA controls the
PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive
an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater
than the PWMnLOAD register (see page 356), then no pulse is ever output.
For comparator A, if the update mode is immediate (based on the CmpAUpd bit in the PWMnCTL
register), then this 16-bit CompA value is used the next time the counter reaches zero. If the update
mode is synchronous, it is used the next time the counter reaches zero after a synchronous
update has been requested through the PWM Master Control (PWMCTL) register (see
page 341). If this register is rewritten before the actual update occurs, the previous value is never
used and is lost.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:0 CompA R/W 0 The value to be compared against the counter.
RO
0
PWMn Compare A (PWMnCMPA)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type
000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
reserved
CompA
