LM3S610 Data Sheet
October 8, 2006 357
Preliminary
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4
These registers contain the current value of the PWM counter (PWM0COUNT controls the PWM
generator 0 block, and so on). When this value matches the load register, a pulse is output; this
can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see
page 360 and 362) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see
page 352). A pulse with the same capabilities is generated when this value is zero.
Bit/Field Name Type Reset Description
31:16 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
15:0 Count RO 0 The current value of the counter.
RO
0
PWMn Counter (PWMnCOUNT)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
Count