LM3S610 Data Sheet
October 8, 2006 353
Preliminary
7:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5 IntCmpBD R/W 0 When 1, an interrupt occurs when the counter matches the
comparator B value and the counter is counting down.
4 IntCmpBU R/W 0 When 1, an interrupt occurs when the counter matches the
comparator B value and the counter is counting up.
3 IntCmpAD R/W 0 When 1, an interrupt occurs when the counter matches the
comparator A value and the counter is counting down.
2 IntCmpAU R/W 0 When 1, an interrupt occurs when the counter matches the
comparator A value and the counter is counting up.
1 IntCntLoad R/W 0 When 1, an interrupt occurs when the counter matches the
PWMnLOAD register.
0 IntCntZero R/W 0 When 1, an interrupt occurs when the counter is 0.
Bit/Field Name Reset Type Description