Pulse Width Modulator (PWM)
350 October 8, 2006
Preliminary
Register 10: PWM0 Control (PWM0CTL), offset 0x040
Register 11: PWM1 Control (PWM1CTL), offset 0x080
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM
generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and
Block Enable mode are all controlled via these registers. The blocks produce the PWM signals,
which can be either two independent PWM signals (from the same counter), or a paired set of
PWM signals with dead-band delays added.
The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2
and PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5 CmpBUpd R/W 0 Same as CmpAUpd but for the comparator B register.
4 C mpAUpd R/ W 0 The Update mode for the comparator A register. If 0,
updates to the register are reflected to the comparator the
next time the counter is 0. If 1, updates to the register are
delayed until the next time the counter is 0 after a
synchro nous update has b een reque sted th rough the PWM
Master Control (PWMCTL) register (see page 341).
3 LoadUpd R/W 0 The Update mode for the load register. If 0, updates to the
register are reflected to the counter the next time the
counter is 0. If 1, updates to the register are delayed until
the next time the counter is 0 after a synchronous update
has been requested through the PWM Master Control
(PWMCTL) register.
2 Debug R/W 0 The behavior of the counter in Debug mode. If 0, the
counter stops running when it next reaches 0, and
continues running again when no longer in Debug mode. If
1, the counter alway s runs .
reserved
RO
0
PWMn Control (PWMnCTL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
CmpBUpd
reserved
Enable
ModeDebug
LoadUpdCmpAUpd
