Pulse Width Modulator (PWM)
344 October 8, 2006
Preliminary
Register 4: PWM Output Inversion (PWM INVERT), offset 0x00C
This register provides a master control of the polarity of the PWM signals on the device pins. The
PWM signals generated by the dead-band block are active High; they can optionally be made
active Low via this register . Disabled PWM channels are also passed through the output inverter (if
so configured) so that inactive channels maintain the correct polarity.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5 PWM5Inv R/W 0 When set, the generated PWM5 signal is inverted.
4 PWM4Inv R/W 0 When set, the generated PWM4 signal is inverted.
3 PWM3Inv R/W 0 When set, the generated PWM3 signal is inverted.
2 PWM2Inv R/W 0 When set, the generated PWM2 signal is inverted.
1 PWM1Inv R/W 0 When set, the generated PWM1 signal is inverted.
0 PWM0Inv R/W 0 When set, the generated PWM0 signal is inverted.
reserved
RO
0
PWM Output Inversion (PWMINVERT)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
PWM5Inv
reserved
PWM0Inv
PWM1InvPWM2Inv
PWM3InvPWM4Inv