LM3S610 Data Sheet
October 8, 2006 341
Preliminary
Register 1: PWM Master Control (PWMCTL), offset 0x000
This register provid es master control over the PWM generation blocks.
Bit/Field Name Type Reset Description
31:3 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
2 GlobalSync 2 R/W 0 Same as GlobalSync0 but for PWM generator 2.
1 GlobalSync 1 R/W 0 Same as GlobalSync0 but for PWM generator 1.
0 GlobalSync 0 R/W 0 Setting this bit causes any queued update to a load or
comparator register in PWM generator 0 to be applied the
next time the cor respondin g counter b ecomes z ero. This b it
automatically clears when the updates have completed; it
cannot be cleared by software.
reserved
RO
0
PWM Master Control (PWMCTL)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W
GlobalSync0GlobalSync1GlobalSync2
reserved