ARM Cortex-M3 Processor Core
34 October 8, 2006
Preliminary
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
2.2 Functional Description
Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of
an ARM Cortex-M3 in detail. However, these features differ based on the
implementation. This section describes the Stellaris im plementation.
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1. As noted in
the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible
in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
2.2.1 Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM
CoreSight™-compliant Serial Wire JT AG Debug Port (SWJ-DP) interface. This means Chapter 12,
“Debug Port,” of the ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris
devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
P rivate Peri pheral
Bus
(internal )
Data
Watchpo int
and Trace
Interrupts
Debug
Sleep
Instrumenta tion
Trace Macrocel l
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
P at c h and
Breakpoint
Memory
Protection
Unit
Ad v. Hig h-
Pe rf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
D ebug P ort
Bus
Mat rix
Adv . Peripheral
Bus
I -c ode bus
D- c ode bus
S ystem bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex- M3
