Pulse Width Modulator (PWM)
338 October 8, 2006
Preliminary
– Write the PWM0CMPA register with a value of 0x0000012B.
7. Set the pulse width of the PWM1 pin for a 75% duty cycle.
– Write the PWM0CMPB register with a value of 0x00000063.
8. Start the timers in PWM generator 0.
– Write the PWM0CTL register with a value of 0x00000001.
9. Enable PWM outputs.
– Write the PWMENABLE register with a value of 0x00000003.
15.4 Register Map
Table 15-2 lists the PWM registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the PWM base address of 0x40028000.
Table 15-1. PWM Register Map (Sheet 1 of 3)
Offset Name Reset Type Description
See
page
PWM Module Control
0x000 PWMCTL 0x00000000 R/W Master control of the PWM module 341
0x004 PWMSYNC 0x00000000 R/W Counter synchronization for the PWM generators 342
0x008 PWMENABLE 0x00000000 R/W Master enable for the PWM output pins 343
0x00C PWMINVERT 0x00000000 R/W Inversion control for the PWM output pins 344
0x010 PWMFAULT 0x00000000 R/W Fault handling for the PWM output pins 345
0x014 PWMINTEN 0x00000000 R/W Interrupt enable 346
0x018 PWMRIS 0x0000 000 0 RO Raw interrupt statu s 347
0x01C PWMISC 0x00000000 R/W1C Interrupt status and clear 348
0x020 PWMSTATUS 0x00000000 RO Value of the Fault input signal 349
PWM Generator 0
0x040 PWM0CTL 0x00000000 R/W Master control of the PWM0 generator block 350
0x044 PWM0INTEN 0x0000 000 0 R/W Interrupt and trig ger ena ble 352
0x048 PWM0RI S 0x0000 0000 RO Raw interrup t st atu s 354
0x04C PWM0ISC 0x00000000 R/W1C Interrupt status and clear 355
0x050 PWM0LOAD 0x00000000 R/W Load value for the counter 356
0x054 PWM0 COUN T 0x00000000 RO Current co unte r valu e 356
0x058 PWM0CMPA 0x00000000 R/W Comparator A value 358
0x05 C PWM0CMPB 0x00000 000 R/W C omparator B value 359
0x060 PWM0GENA 0x00000000 R/W Controls PWM generator A 360