LM3S610 Data Sheet
October 8, 2006 337
Preliminary
timers in those blocks are synchronized, though this is not required in order for this mechanism to
function prope rly.
15.2.7 Fault Conditions
There are two external conditions that affect the PWM block; the signal input on the Fault pin and
the stalling of the controller by a debugger. There are two mechanisms available to handle such
conditions: the output signals can be forced into an inactive state and/or the PWM timers can be
stopped.
Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal
to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an
extended period of time, this keeps the output signal from driving the outside world in a dangerous
manner during the fault condition. A fault condition can also generate a controller interr upt.
Each PWM generator can also be configured to stop counting during a stall condition. The user
can select for the counters to run until they reach zero then stop, or to continue counting and
reloading. A stall condition does not generate a controller interrupt.
15.2.8 Output Control Block
With each PWM generator block producing two raw PWM signals, the output control block takes
care of the final conditioning of the PWM signals before they go to the pins. Via a single register,
the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for
example, to perform commutation of a brushless DC motor with a single register write (and without
modifying the individual PWM generators, which are modified by the feedback control loop).
Similarly, fault control can disable any of the PWM signals as well. A final inversion can be applied
to any of the PWM signals, making them active Low instead of the default active High.
15.3 Initialization and Configuration
The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and
with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example
assumes the system clock is 20 MHz.
1. Enable the PWM clock by writing a value of 0x00100000 to the RCGC0 register in the System
Control module.
2. In the GPIO module, enable the appropriate pins for their alternate function using the
GPIOAFSEL register.
3. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module
to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000).
4. Configure the PWM generator for countdown mode with immediate updates to the
parameters.
– Write the PWM0CTL register with a value of 0x00000000.
– Write the PWM0GENA register with a value of 0x0000008C.
– Write the PWM0GENB register with a value of 0x0000080C.
5. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM
clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per
period. Use this value to set the PWM0LOAD re giste r. In Count-Down mode, set the LOAD
field in the PWM0LOAD register to the requested period minus one.
– Write the PWM0LOAD register with a value of 0x0000018F.
6. Set the pulse width of the PWM0 pin for a 25% duty cycle.
