Pulse Width Modulator (PWM)
336 October 8, 2006
Preliminary
15.2.4 Dead-Band Generator
The two PWM signals produced by the PWM generator are passed to the dead-band generator . If
disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is
lost and two PWM signals are generated based on the first PWM signal. The first output PWM
signal is the input signal with the rising edge delayed by a programmable amount. The second
output PWM signal is the inversion of the input signal with a programmable delay added between
the falling edge of the input signal and the rising edge of this new signal.
This is therefore a pair of active High signals where one is always High, except for a
programmable amount of time at transitions where both are Low. These signals are therefore
suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current
from damaging the power electronics. Figure 15-5 shows the effect of the dead-band generator on
an input PWM signal.
Figure 15-5. PWM Dead-Band Generator
15.2.5 Interrupt/ADC-Trigger Selector
The PWM generator also takes the same four (or six) counter events and uses them to generate
an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a
source for an interrupt; when any of the selected events occur, an interrupt is generated.
Additionally, the same event, a different event, the same set of events, or a different set of events
can be selected as a source for an ADC trigger; when any of these selected events occur , an ADC
trigger pulse is generated. The selection of events allows the interrupt or ADC trigger to occur at a
specific position within the PWM signal. Note that interrupts and ADC triggers are based on the
raw events; delays in the PWM signal edges caused by the dead-band generator are not taken
into account.
15.2.6 Synchronization Methods
There is a global reset capability that can synchronously reset any or all of the counters in the
PWM generator. If multiple PWM generators are configured with the same counter load value, this
can be used to guarantee that they also have the same count value (this does imply that the PWM
generators must be configured before they are synchronized). With this, more than two PWM
signals can be produced with a known relationship between the edges of those signals since the
counters always have the same values.
The counter load values and comparator match values of the PWM generator can be updated in
two ways. The first is immediate update mode, where a new value is used as soon as the counter
reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and
overly short or overly long output PWM pulses are prevented.
The other update method is synchronous, where the new value is not used until a global
synchronized update signal is asserted, at which point the new value is used as soon as the
counter reaches zero. This second mode allows multiple items in multiple PWM generators to be
updated simultaneously without odd effects during the update; everything runs from the old values
until a point at which they all run from the new values. The Update mode of the load and
comparator match values can be individually configured in each PWM generator block. It only
makes sense to use the synchronous update mechanism across PWM generator blocks when the
Input
PWMA
PWMB
Rising Edge
Delay
Falling Edge
Delay
