Inter-Integrated Circuit (I2C) Interface
332 October 8, 2006
Preliminary
Register 16: I
2
C Slave Interrupt Clear (I2CSICR), offset 0x018
This register clears the raw interrupt.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
0 IC WO 0 This bit controls the clearing of the raw interrupt. A write of
1 clears the interrupt; otherwise a write of 0 has no affect on
the interrupt state. A read of this register returns no
meaningf ul data .
reserved
RO
0
I2C Slave Interrupt Clear (I2CSICR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
IC
reserved