LM3S610 Data Sheet
October 8, 2006 331
Preliminary
Register 15: I
2
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014
This register specifies whether an interrupt was signaled.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
0 MIS RO 0 This bit specifies the raw interrupt state (after masking) of
the I
2
C slave block. If set, an interrupt was signaled;
other wise, an inter rupt has not be en gene rated since the bit
was last cleared.
reserved
RO
0
I2C Slave Masked Interrupt Status (I2CSMIS)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
00000000000000 0
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
MIS
reserved