Inter-Integrated Circuit (I2C) Interface
330 October 8, 2006
Preliminary
Register 14: I
2
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010
This register specifies whether an interrupt is pending.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
0 RIS RO 0 This b it spec ifies the raw inte rrupt st ate (prio r to mas king) of
the I
2
C slave block. If set, an interrupt is pending;
otherwise, an interrupt is not pending.
reserved
RO
0
I2C Slave Raw Interrupt Status (I2CSRIS)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
00000000000000 0
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RIS
reserved