LM3S610 Data Sheet
October 8, 2006 329
Preliminary
Register 13: I
2
C Slave Interrupt Mask (I2CSIMR), offset 0x00C
This register controls whether a raw interrupt is promoted to a controller interrupt.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indeterminat e value, and should
never be changed.
0 IM R/W 0 This bit controls whether a raw interrupt is promoted to a
controller interrupt. If set, the interrupt is not masked and
the interrupt is promoted; otherwise, the interrupt is
masked.
reserved
RO
0
I2C Slave Interrupt Mask (I2CSIMR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
IM
reserved