LM3S610 Data Sheet
October 8, 2006 327
Preliminary
0 RREQ RO 0 Receive Request
This bit specifies the status of the I
2
C slave with regar ds
to outstanding receive requests. If set, the I
2
C unit has
outstanding receive data from the I
2
C master and uses
clock stretching to delay the master until the data has
been read from the I2CSDR register. Otherwise, no
receive data is outstanding.
Write-Only Control Register
31:1 reserved RO 0 Reserved bits return an indeterminat e value, and should
never be changed.
0 DA WO 0 Device Active
1=Enables the I
2
C slave operation.
0=Disables the I
2
C slave operation.
Bit/Field Name Type Reset Description