Inter-Integrated Circuit (I2C) Interface
326 October 8, 2006
Preliminary
Register 11: I
2
C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and two status bits when read.
The read-only Status register consists of two bits: the RREQ bit and the TREQ bit. The Receive
Request (RREQ) bit indicate s that the Stell aris I
2
C device has received a data byte from an I
2
C
master. Read one data byte from the I2C Slave Data (I2CSDR) register. The Transmit
Request (TREQ) bit indicate s that the Stell aris I
2
C device is addressed as a Slave Transmitter.
Write one data byte into theI2C Slave Data (I2CSDR) regis t e r.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I
2
C slave operati on.
Bit/Field Name Type Reset Description
Read-Only Status Register
31:2 reserved RO 0 Reserved bits return an indeterminat e value, and should
never be changed.
1 TREQ RO 0 This bit specifies the s t a te of the I
2
C slave with regards to
outst anding transmit request s. I f set, th e I
2
C uni t has b een
addressed as a slave transmitter and uses clock
stretching to delay the master until data has been written
to the I2CSDR regist er . Otherwise , there is no out stand ing
transmit request.
reserved
RO
0
I2C Slave Status Register (I2CSCSR): Read
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RREQ
reserved
TREQ
reserved
RO
0
I2C Slave Control Register (I2CSCSR): Write
Offset 0x004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO WO
DA
reserved