LM3S610 Data Sheet
October 8, 2006 325
Preliminary
14.6 Register Descriptions (I
2
C Slave)
The remainder of this section lists and describes the I
2
C slave registers, in numerical order by
address offset. See also “Register Descriptions (I2C Master)” on page 311.
Register 10: I
2
C Slave Own Address (I2CSOAR), offset 0x000
This register consists of seven address bits that identify the Stellaris I
2
C device on the I
2
C bus.
Bit/Field Name Type Reset Description
31:7 reserved RO 0 Reserved bits return an indeterminat e value, and should
never be changed.
6:0 OAR R/W 0 I
2
C Slave Own Address
This field specifies bits A6 through A0 of the slave
address.
reserved
RO
0
I2C Slave Own Address Register (I2CSOAR)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W
reserved
OAR