Inter-Integrated Circuit (I2C) Interface
324 October 8, 2006
Preliminary
Regist er 9: I
2
C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave) and sets the interface for test mode loopback.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
5SFER/W0I
2
C Slave Function Enable
This bit specifies whether the interface may operate in
Slave mode. If set, Slave mode is enabled; otherwise,
Slave mode is disabled.
4MFER/W0I
2
C Master Function Enable
This bit specifies whether the interface may operate in
Master mod e. If set, Mas te r mode is enabl ed; oth erw is e,
Master mod e is dis ab led an d th e interface clock is di sab le d.
3:1 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
0 LPBK R/W 0 I
2
C Loopback
This bit specifies whether the interface is operating
normally or in Loopback mode. If set, the device is put in a
test mode loopback configuratio n; othe rw is e, the dev ic e
operates normally.
reserved
RO
0
I2C Master Configuration (I2CMCR)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO R/W R/W RO RO RO R/W
LPBK
reserved
MFE
SFE
reserved