Inter-Integrated Circuit (I2C) Interface
320 October 8, 2006
Preliminary
Regist er 5: I
2
C Master Interrupt Mask (I2CMIMR), offset 0x010
This register controls whether a raw interrupt is promoted to a controller interrupt.
Bit/Field Name Type Reset Description
31:1 reserved RO 0 Reserved bits return an indetermi nate value, and should
never be changed.
0 IM R/W 0 This bit controls whether a raw interrupt is promoted to a
controller interrupt. If set, the interrupt is not masked and
the interrupt is promoted; otherwise, the interrupt is
masked.
reserved
RO
0
I2C Master Interrupt Mask (I2CMIMR)
Offset 0x010
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO R/W
IM
reserved