LM3S610 Data Sheet
October 8, 2006 319
Preliminary
Regist er 4: I
2
C Master Timer Period (I2CMTPR), offset 0x00C
This register specifies the period of the SCL clock
Bit/Field Name Type Reset Description
31:8 reserve d RO 0 Reserved bi ts return an indeterminate value, and s hould never
be changed.
7:0 TPR R/W 0x1 This field specifies the period of the SCL clock.
SCL_PRD = 2*(1 + TPR)*(SCL_LP +
SCL_HP)*CLK_PRD
where:
SCL_PRD is the SCL line period (I
2
C clock).
TPR is the Timer Period register value (range of 1 to 255).
SCL_LP is the SCL Low period (fixed at 6).
SCL_HP is the SCL High period (fixed at 4).
reserved
RO
0
I2C Master Timer Period (I2CMTPR)
Offset 0x00C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000001
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
reserved
TPR