Inter-Integrated Circuit (I2C) Interface
314 October 8, 2006
Preliminary
4 ARBLST R 0 This bit sp ecifies the result of bus arbitra tion. If set, the controlle r
lost arbit rati on; oth erw is e, the co ntrol le r won arbi trat ion .
3 DATACK R 0 This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data
was acknowledged.
2 ADRACK R 0 This bit specifies the result of the last address operation. If set,
the transmitted address was not acknowledged; otherwise, the
address was acknowledged.
1 ERROR R 0 This bit specifies the result of the last bus operation. If set, an
error occurred on the last operation; otherwise, no error was
detected. The error can be from the slave address not being
acknowledged, the transmit data not being acknowledged, or
because the controller lost arbitration.
0 BUSY R 0 This bit specifies the st ate of the contro ller . If set, the contro ller is
busy; otherwise, the controller is idle. When the BUSY bit is set,
the other status bits are not valid.
Write-Only Control Register
31:7 reserved RO 0 Reserved bits return an indeterminate value, and should never
be chang ed.
6-4 reserved W 0 Write reserved.
3 ACK W 0 When set, causes received data byte to be acknowledged
automatic ally by the ma ster. See field deco ding in Table 14-3 on
page 315.
2 STOP W 0 When set, causes the generation of the STOP condition. See
field decoding in Table 14-3.
1 START W 0 When set, causes the generation of a START or repeated
START condition. See field decoding in Table 14-3.
0 RUN W 0 When set, allows the master to send or receive data. See field
decoding in Table 14-3.
Bit/Field Name Type Reset Description