Inter-Integrated Circuit (I2C) Interface
312 October 8, 2006
Preliminary
Regist er 1: I
2
C Master Slave Address (I2CMSA), offset 0x000
This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which
determines if the next operation is a Receive (High), or Send (Low).
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:1 SA R/W 0 I
2
C Slave Address
This field specifies bits A6 through A0 of the slave address.
0 R/S R/W 0 Receive/Send
The R/S bit specifies if the next operation is a Receive (High) or
Send (Low).
0: Send
1: Receive
reserved
RO
0
I2C Master Slave Address (I2CMSA)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
R/S
reserved
SA