LM3S610 Data Sheet
October 8, 2006 311
Preliminary
14.4 Register Map
Table 14-2 li st s the I
2
C registers. All addresses given are relative to the I
2
C base addresses for the
master and slave:
I
2
C Master: 0x40020000
I
2
C Slave: 0x40020800
14.5 Register Descriptions (I
2
C Master)
The remainder of this section lists and describes the I
2
C master registers, in numerical order by
address offset. See also “Register Descriptions (I2C Slave)” on page 325.
Table 14-2. I
2
C Register Map
Offset Name Reset Type Description
See
page
0x000 I2CMSA 0x00000000 R/W Master slave address 312
0x004 I2CMCS 0x00000000 R/W Master control/status 313
0x008 I2CMDR 0x00000000 R/W Master data 318
0x00 C I2CMTPR 0x000 00001 R/ W Master timer period 319
0x010 I2CMIMR 0x00000000 R/W Master interrupt mask 320
0x014 I2CMRIS 0x00000000 RO Master raw interrupt status 321
0x018 I2CMMIS 0x00000000 RO Master masked interrupt status 321
0x01 C I2C MICR 0x00000 000 WO Master interrupt clear 322
0x020 I2CMCR 0x00000000 R/W Master configuration 323
0x000 I2CSOAR 0x00000000 R/W Slave address 325
0x004 I2CSCSR 0x00000000 RO Slave control/status 326
0x008 I2CSDR 0x00000000 R/W Slave data 328
0x00C I2CSIMR 0x00000000 R/W Slave interrupt mask 329
0x010 I2CSRIS 0x00000000 RO Slave raw interrupt status 330
0x014 I2CSMIS 0x00000000 RO Slave masked interrupt status 331
0x018 I2CSICR 0x00000000 WO Slave interrupt clear 332