LM3S610 Data Sheet
October 8, 2006 301
Preliminary
14 Inter-Integrated Circuit (I
2
C) Interface
The Inter-Integrated Circuit (I
2
C) bus provides bi-directional data transfer through a two-wire
design (a serial data line SDL and a serial clock line SCL).
The I
2
C bus interfaces to external I
2
C devices such as serial memory (RAMs and ROMs),
networking devices, LCDs, tone generators, and so on. The I
2
C bus may also be used for system
testing and diagnostic purposes in product development and manufacture.
The Stellaris I
2
C module provides the ability to communicate to other IC devices over an I
2
C bus.
The I
2
C bus supports devices that can both transmit and receive (write and read) data.
Device s o n th e I
2
C bus can be designated as either a master or a slave. The I
2
C module supports
both sending and receiving data as either a master or a slave, and also supports the simultaneous
operation as both a master and a slave. The four I
2
C modes are: Master Transmit, Master
Receive, Slave Transmit, and Slave Receive.
The Stellaris I
2
C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps).
Both the I
2
C master and slave can generate interrupts. The I
2
C master generates interrupts when
a transmit or receive operation completes (or aborts due to an error). The I
2
C slave generates
interrupts when data has been sent or requested by a master.
14.1 Block Diagram
Figure 14-1. I
2
C Block Diagram
14.2 Functional Description
The I
2
C module is comprised of both a master and slave function. The master and slave functions
are implemented as separate peripherals. The I
2
C module must be connected to bi-directional
Open-Drain pads. A typical I
2
C bus configuration is shown in Figure 14-2.
See “I2C Timing” on page 382 for I
2
C timing diagrams.
I
2
C I/O Select
I
2
C Master Core
Interrupt
I
2
C Slave Core
I2CSCL
I2CSDA
I2CSDA
I2CSCL
I2CSDA
I2CSCL
I2CMSA
I2CMCS
I2CMDR
I2CMTPR
I2CMIMR
I2CMRIS
I2CMICR
I2CMCR
I2CSOAR
I2CSCSR
I2CSDR
I2CSIM
I2CSRIS
I2CSMIS
I2CSICRI2CMMIS
I
2
C Control