Synchronous Serial Interface (SSI)
288 October 8, 2006
Preliminary
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
Bit/Field Name Type Reset Description
31:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
1 RTIC W1C 0 SSI Receive Time-Out Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear
0: No effect on interrupt.
1: Clears interrupt.
reserved
RO
0
SSI Interrupt Clear (SSIICR)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO W1C W1C
reserved
RORIC
RTIC