Synchronous Serial Interface (SSI)
286 October 8, 2006
Preliminary
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018
The SSIRIS register is the raw interrupt status register. On a read, this register gives the current
raw status value of the corresponding interrupt prior to masking. A write has no effect.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 TXRIS RO 1 SSI Transmit FIFO Raw Interrupt Status
Indicates that the transmit FIFO is half full or less, when set.
2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status
Indicates that the re ceive FIFO is half full or more, when set.
1 RTRIS RO 0 SSI Receive Time-Ou t Raw Interrupt Status
Indicates that the receive time-out has occurred, when set.
0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status
Indicates that the receive FIFO has overflowed, when set.
reserved
RO
0
SSI Raw Interrupt Status (SSIRIS)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000001000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
RORRIS
RTRISRXRIS
TXRIS