LM3S610 Data Sheet
October 8, 2006 285
Preliminary
Regist er 6: SSI Interrupt Mask (SSIIM), offset 0x 014
The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits
are cleared to 0 on reset.
On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to
the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the
corresponding mask.
Bit/Field Name Type Reset Description
31:4 reserved RO 0 Reserved bits return an indeterminate value, and should
never be change d.
3 TXIM R/W 0 SSI Transmit FIFO Interrupt Mask
0: TX FIFO half-full or less condition interrupt is masked.
1: TX FIFO half-full or less condition interrupt is not masked.
2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask
0: RX FIFO half-full or more condition interrupt is masked.
1: RX FIFO half-full or more condition interrupt is not masked.
1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask
0: RX FIFO time-out interrupt is masked.
1: RX FIFO time-out interrupt is not masked.
0 RORIM R/W 0 SSI Receive Overrun Interrupt Mask
0: RX FIFO overrun interrupt is masked.
1: RX FIFO overrun interrupt is not masked.
reserved
RO
0
SSI Interrupt Mask (SSIIM)
Offset 0x014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
reserved
RORIM
RTIMRXIM
TXIM