Synchronous Serial Interface (SSI)
276 October 8, 2006
Preliminary
3. Write t he SSICPSR register with a value of 0x00000002.
4. Write t he SSICR0 register with a value of 0x000009C7.
5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1.
13.4 Register Map
Table 13-1 lists the SSI registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the SSI base address of 0x40008000.
Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the
control registers are reprogrammed.
Table 13-1. SSI Register Map
Offset Name Reset Type Description
See
page
0x000 SSICR0 0x00000000 RW Control 0 278
0x004 SSICR1 0x00000000 RW Control 1 280
0x008 SSIDR 0x00000000 RW Data 282
0x00C SSISR 0x00000003 RO Status 283
0x010 SSICPSR 0x00000000 RW Clock prescale 284
0x014 SSIIM 0x00000000 RW Interrupt mask 285
0x018 SSIRIS 0x0000 000 8 RO Raw interrupt statu s 286
0x01C SSIMIS 0x00000000 RO Masked interrupt status 287
0x020 SSIICR 0x00000000 W1C Interrupt clear 288
0xFD0 SSIPeriphID4 0x00000000 RO Peripheral identification 4 289
0xFD4 SSIPeriphID5 0x00000000 RO Peripheral identification 5 290
0xFD8 SSIPeriphID6 0x00000000 RO Peripheral identification 6 291
0xFDC SSIPeriphID7 0x00000000 RO Peripheral identification 7 292
0xFE0 SSIPeriphID0 0x00000022 RO Peripheral identification 0 293
0xFE4 SSIPeriphID1 0x00000000 RO Peripheral identification 1 294
0xFE8 SSIPeriphID2 0x00000018 RO Peripheral identification 2 295
0xFEC SSIPeriphID3 0x00000001 RO Peripheral identification 3 296
0xFF0 SSIPCellID0 0x0000000D RO PrimeCell identification 0 2 97
0xFF4 SSIPCellID1 0x000000F0 RO PrimeCell identification 1 298
0xFF8 SSIPCellID2 0x00000005 RO PrimeCell identification 2 299
0xFFC SSIPCellID3 0x000000B1 RO PrimeCell identification 3 300
