LM3S610 Data Sheet
October 8, 2006 271
Preliminary
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1
In this configuration, during idle periods:
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbi trar il y force d Low
When the SSI is configured as a master, it enables the SSIClk pa d
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx outp ut is ena ble d.
After a further one half SSIClk period, both master and slave valid data is enabled onto their
respective transmission lines. At the same time, the SSIClk is enabled with a rising edge
transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSIClk
signal.
In the case of a single word transfer, after all bits have been transferred, the SSIFss line is
returned to its idle High state one SSIClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data
words and termination is the same as that of the single word transfer.
13.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0
Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and
SPH=0 are shown in Figure 13-7 and Figure 13-8.
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0
4to16bits
SSIClk
SSIFss
SSIRx
SSITx
Q
MSB
Q
MSB
LSB
LSB
4to16bits
SSIClk
SSIFss
SSIRx
SSITx
QMSB
MSB LSB
LSB
