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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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LM3S610 Data Sheet
October 8, 2006 27
Preliminary
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S610 microcontroller. The
chapter number in parenthesis indicates where that feature is discussed in detail. Ordering and
support information can be found in “Ordering and Contact Information” on page 395.
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (Section 2 on page 33)
All members of the Stellaris product family, including the LM3S610 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core
for a high-performance, low-cost platform that meets the needs of minimal memory
implementation, reduced pin count, and low power consumption, while delivering outstanding
computational performance and exceptional system response to interrupts.
Section 2, “ARM Cortex-M3 Processor Core,” on page 33 provides an overview of the ARM core;
the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 Nested V ectored Interrupt Controller (NVIC)
The LM3S610 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stor ed to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed
without the overhead of state saving and restoration. Software can set eight priority levels on 7
exceptions (system handlers) and 26 interrupts.
Section 4, “Interrupts,” on page 38 provides an overview of the NVIC controller and the interrupt
map. Exce ptions and interrupts are detailed in the AR M® Cortex ™-M3 Techn ic al Refe renc e
Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S610 controller features Pulse Width Modulation (PWM)
outputs.
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power
supplie s a nd moto r contr ol .
On the LM3S610, PWM motion control functionality can be achieved through dedicated, flexible
motion control hardware (the PWM pins) or through the motion control features of the
general-purpose timers (using the CCP pins).
PWM Pins (Section 15 on page 333)
The LM3S610 PWM module consists of three PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the
pins.
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