LM3S610 Data Sheet
October 8, 2006 265
Preliminary
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC
The UARTPCellIDn registers are hard-coded and the fields within the registers determine the
reset values.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 CID3 RO 0xB1 UART PrimeCell ID Register[31:24]
Provides software a standard cross-peripheral identification
system.
reserved
RO
0
UART Primecell Identification 3 (UARTPCellID3)
Offset 0xFFC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000010110001
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
CID3