Architectural Overview
26 October 8, 2006
Preliminary
1.3 High-Level Block Diagram
Figure 1-1. Stellaris High-Level Block Diagram
DCode bus
APB Bridge SRAM
ICode bus
ARM Cortex-M3
Flash
(including Nested
Vectored Interrupt
Controller (NVIC))
Memory
Peripherals
LMI JTAG
Test Access Port
(TAP)
Controller
System
Control
& Clocks
Universal
Asynchronous
Receivers/
Transmitters
(UARTs)
Synchronous
Serial
Interface
(SSI)
General-Purpose
Timers
Inter
Integrated
Circuit
(I2C)
LM3S610
General-Purpose
Input/Outputs
(GPIOs)
System
Peripherals
Serial
Communications
Peripherals
Pulse
Width
Modulator
(PWM)
Motor
Control
Peripherals
Analog
Peripherals
Analog-to-
Digital
Converter
(ADC)
Temperature
Sensor
Watchdog
Timer
Peripheral Bus