Universal Asynchronous Receivers/Transmitters (UARTs)
252 October 8, 2006
Preliminary
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040
The UARTMIS register is the masked interrupt status register. On a read, this register gives the
current masked status value of the corresponding interrupt. A write has no effect.
Bit/Field Name Type Reset Description
31:11 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
10 OEMIS RO 0 UART Overrun Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
9 BEMIS RO 0 UART Break Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
8 PEMIS RO 0 UART Parity Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
7 FEMIS RO 0 UART Framing Error Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
5 TXMIS RO 0 UART Transmit Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
4 RXMIS RO 0 UART Receive Masked Interrupt Status
Gives the ma sk ed inte rrup t state of this interrupt.
3:0 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
reserved
RO
0
UART Masked Interrupt Status (UARTMIS)
Offset 0x040
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
OEMIS
reserved
BEMIS
PEMIS
FEMIS RTMIS
TXMIS RXMIS
reserved