Universal Asynchronous Receivers/Transmitters (UARTs)
248 October 8, 2006
Preliminary
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to
define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receivin g the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an
interrupt at the half-way mark.
Bit/Field Name Type Reset Description
31:6 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
5:3 RXIFLSEL R/W 0X2 UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
000: RX FIFO ≥ 1/8 full
001: RX FIFO ≥ 1/4 full
010: RX FIFO ≥ 1/2 full (default)
011: RX FIFO ≥ 3/4 full
100: RX FIFO ≥ 7/8 full
101-111: Reserved
2:0 TXIFLSEL R/W 0X2 UART Transmit Interrupt FIFO Level Select
The trigger points for the transmit interrupt are as follows:
000: TX FIFO ≤ 1/8 full
001: TX FIFO ≤ 1/4 full
010: TX FIFO ≤ 1/2 full (default)
011: TX FIFO ≤ 3/4 full
100: TX FIFO ≤ 7/8 full
101-111: Reserved
reserved
RO
0
UART Interrupt FIFO Level Select (UARTIFLS)
Offset 0x034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000010010
RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W
reserved
TXIFLSEL
RXIFLSEL
