LM3S610 Data Sheet
October 8, 2006 247
Preliminary
Register 7: UART Control (UARTCTL), offset 0x030
The UARTCTL register is the control register. All the bits are cleared on reset except for the
Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1.
To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration
change in the module, the UARTEN bit must be cleared before the configuration changes are
written. If the UART is disabled during a transmit or receive operation, the current transaction is
completed prior to the UART stopping.
Bit/Field Name Type Reset Description
31:10 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
9 RXE R/W 1 UART Receive Enable
If this bit is set to 1, the receive section of the UART is enabled.
When the UART is disabled in the middle of a receive, it
completes the current character before stopping.
8 TXE R/W 1 UART Transmit Enable
If this bit is s et to 1, the tran sm it se cti on of the UAR T i s en abl ed.
When the UART is disabled in the middle of a transmission, it
completes the current character before stopping.
7 LBE R/W 0 UART Loop Back Enable
If this bit is set to 1, the UnTX path is fed through the UnRX path.
6:1 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
0 UARTEN R/W 0 UART Enable
If this bit is set to 1, the UART is enabled. When the UART is
disabled in the middle of transmission or reception, it completes
the current character before stopping.
RO
0
UART Control (UARTCR)
Offset 0x030
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000001100000000
RO RO RO RO RO R/W R/W R/W RO RO RO RO RO RO R/W
reserved
reserved
RXE
TXE
LBE
UARTEN
reserved
