LM3S610 Data Sheet
October 8, 2006 245
Preliminary
Register 6: UART Line Control (UARTLCRH), offset 0x02C
The UARTLCRH register is the line control register. Serial parameters such as data length, parity
and stop bit selection are implemented in this register.
When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register
must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH
register.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7 SPS R/W 0 UART Stick Parity Select
When bits 1, 2 and 7 of UARTLCRH are set, the parity bit is
transmitt ed an d chec ked a s a 0. W hen b it s 1 and 7 a re set a nd 2
is cleared, the parity bit is transmitted and checked as a 1.
When this bit is cleared, stick parity is disabled.
6:5 WLEN R/W 0 UART Word Length
The bits ind ic ate the number of data bi t s tra ns mitted or receiv ed
in a frame as follows:
0x3: 8 bits
0x2: 7 bits
0x1: 6 bits
0x0: 5 bits (default)
4 FEN R/W 0 UART Enable FIFOs
If this bit is set to 1, transmit and receive FIFO buffers are
enabled (FIFO mode).
When cleared to 0, FIFOs are disabled (Character mode). The
FIFOs become 1-byte-deep holding registers.
3 STP2 R/W 0 UART Two Stop Bits Select
If this bit is set to 1, two stop bits are transmitted at the end of a
frame. The receive logic does not check for two stop bits being
received.
reserved
RO
0
UART Line Control (UARTLCRH)
Offset 0x02C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
SPS
reserved
WLEN
FEN STP2 EPS PEN BRK
