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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
LM3S610 Data Sheet
October 8, 2006 241
Preliminary
Register 3: UART Flag (UARTFR), offset 0x018
The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and
TXFE and RXFE bits are 1.
Bit/Field Name Type Reset Description
31:8 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
7 TXFE RO 1 UART Transmit FIFO Empty
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FI FO is dis abled (FEN is 0), t his b it is set when t he tran smit
holding register is empty.
If the FIFO is e nabled (FEN is 1), this bit is set when th e transm it
FIFO is empty.
6 RXFF RO 0 UART Receive FIFO Full
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the receive holding
register is full.
If the FIFO is enabled, this bit is set when the receive FIFO is
full.
5 TXFF RO 0 UART Transmit FIFO Full
The meani ng of this bit depends on the st ate of the FEN bit in the
UARTLCRH register.
If the FIFO is disabled, this bit is set when the transmit holding
register is full.
If the FIFO is enabled, this bit is set when the transmit FIFO is
full.
reserved
RO
0
UART Flag (UARTFR)
Offset 0x018
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000010010000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
reserved
TXFE
RXFF
TXFF
RXFE BUSY
reserved
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