Universal Asynchronous Receivers/Transmitters (UARTs)
240 October 8, 2006
Preliminary
2 BE RO 0 UART Break Error
This bit is se t to 1 w h en a break condition is de tec ted, indicating
that the rece ived data input was held Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded in to the FIFO. The next character is only enabled after
the receive data input goes to a 1 (marking state) and the next
valid st art bit is receiv ed .
1 PE RO 0 UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
This bit is cleared to 0 by a write to UARTECR.
0 FE RO 0 UART Framing Error
This bit is set to 1 when the received character does not have a
valid stop bit (a valid stop bit is 1).
This bit is cleared to 0 by a write to UARTECR.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
Write-Only Error Clear (UARTECR) Register
31:8 reserved WO 0 Reserved bits return an indeterminate value, and should never
be changed.
7:0 DATA WO 0 A write to this register of any data clears the framing, parity,
break and overrun flags.
Bit/Field Name Type Reset Description