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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
LM3S610 Data Sheet
October 8, 2006 237
Preliminary
Register 1: UART Data (UARTDR), offset 0x000
This register is the data register (the interface to the FIFOs).
When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs
are disabled, data is stored in the transmitter holding register (the bottom word of the transmit
FIFO). A write to this register initiates a transmission from the UART.
For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity
and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and
status are stored in the receiving holding register (the bottom word of the receive FIFO). The
received data can be retrieved by reading this register.
Bit/Field Name Type Reset Description
31:12 reserved RO 0 Reserved bits return an indeterminate value, and should never
be changed.
11 OE RO 0 UART Overrun Error
1=New data was received when the FIFO was full, resulting in
data loss.
0=There has been no data loss due to a FIFO overrun.
10 BE RO 0 UART Break Error
This bit is se t to 1 w h en a break condition is de tec ted, indicating
that the receive data input was he ld Low for longer than a full-
word transmission time (defined as start, data, parity, and stop
bits).
In FIFO mode, this error is associated with the character at the
top of the FIFO. When a break occurs, only one 0 character is
loaded in to the FIFO. The next character is only enabled after
the received data input goes to a 1 (marking state) and the next
valid st art bit is receiv ed .
9 PE RO 0 UART Parity Error
This bit is set to 1 when the parity of the received data character
does not match the parity defined by bits 2 and 7 of the
UARTLCRH register.
In FIFO mode, this error is associated with the character at the
top of the FIFO.
reserved
RO
0
UART Data (UARTDR)
Offset 0x000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000000
RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W
FE
reserved
DATA
PEBE
OE
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