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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
Universal Asynchronous Receivers/Transmitters (UARTs)
232 October 8, 2006
Preliminary
bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the
control registers. See Figure 12-2 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid
start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are
also performed, and their status accompanies the data that is written to the receive FIFO.
Figure 12-2. UART Character Frame
12.2.2 Baud-Rate Generation
The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part.
The number formed by these two values is used by the baud-rate generator to determine the bit
period. Having a fractional baud-rate divider allows the UART to generate all the standard baud
rates.
The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) reg is t er
(see page 243) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate
Divisor (UARTFBRD) register (see page 244). The baud-rate divisor (BRD) has the following
relationship to th e system clock (where BRDI is the integer part of the BRD and BRDF is the
fractional part, separated by a decimal place.):
BRD = BRDI + BRDF = SysClk / (16 * Baud Rate)
The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD
register) can be calculated by taking the fractional part of the baud-rate divisor , multiplying it by 64,
and adding 0.5 to account for rounding errors:
UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5)
The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as
Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for
error detection during receive operations.
Along with the UART Line Control, High Byte (UARTLCRH) register (see page 245), the
UARTIBRD and UARTFBRD registers form an internal 30-bit register . This internal register is only
updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate
divisor must be followed by a write to the UARTLCRH register for the changes to take effect.
To update the baud-rate registers, there are four possible sequences:
UARTIBRD write, UARTFBRD write, and UARTLCRH write
UARTFBRD write, UARTIBRD write, and UARTLCRH write
UARTIBRD write and UARTLCRH write
UARTFBRD write and UARTLCRH write
1
0
5-8 data bits
LSB
MSB
Parity bit
if enabled
1-2
stop bits
UnTX
n
Start
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