LM3S610 Data Sheet
October 8, 2006 23
Preliminary
– False-start-bit detection
– Line-break generation and detection
ADC
– Single- and differential-input configurations
– Two 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 500 thousand samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, PWM or GPIO)
I
2
C
– Master and slave receive and transmit operation with transmission speed up to 100 Kbps in
Standard mode and 400 Kbps in Fast mode
– Interrupt generation
– Master with arbitration and clock synchronizatio n, multimaster support, and 7-bit
addressing mode
PWM
– Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output freque ncy controlled by a 16-bit load value
• Load valu e updates can be synchronize d
• Produces output signals at zero and load value
– Two comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter
and comparator output signals
• Produces two independe nt PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving
a half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
