LM3S610 Data Sheet
October 8, 2006 227
Preliminary
Register 24: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x064
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer.
This register is 4-bits wide and contains information for one possible sample. This register’s bit
fields are as shown in the diagram below. Bit field definitions are the same as those in the
ADCSSCTL0 register (see page 218) but are for Sample Sequencer 3.
Register 25: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8
This register contains the conversion results for samples collected with Sample Sequencer 3.
Reads of this register return the conversion result data. If the FIFO is not properly handled by
software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT
registers.
Bit fields and definitions are the same as ADCSSF IFO0 (see page 220) but are for FIFO 3.
Register 26: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC
This register provides a window into the Sample Sequencer FIFO 3, providing full/empty status
information as well as the positions of the head and tail pointers. The reset value of 0x100
indicates an empty FIFO.
This register has the same bit fields and definitions as ADCSSFSTAT0 (see page 221) but is for
FIFO 3.
reserved
RO
0
ADC Sample Sequence Control 3 (ADCSSCTL3)
Offset 0x0A4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1514131211109876543210
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
000000000000010
RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W
TS0 IE0
END0 D0
reserved
