LM3S610 Data Sheet
October 8, 2006 225
Preliminary
Register 20: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between.
This register is 16-bits wide and contains information for four possible samples. This register’s bit
fields are as shown in the diagram below. Bit field definitions are the same as those in the
ADCSSCTL0 register (see page 218) but are for Sample Sequencer 2.
Register 21: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
This register contains the conversion results for samples collected with Sample Sequencer 2.
Reads of this register return conversion result data in the order sample 0, sample 1, and so on,
until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow
conditions are registered in the ADCOSTAT and ADCUSTAT regi sters.
Bit fields and definitions are the same as ADCSSF IFO0 (see page 220) but are for FIFO 2.
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C
This register provides a window into the Sample Sequencer FIFO 2, providing full/empty status
information as well as the positions of the head and tail pointers. The reset value of 0x100
indicates an empty FIFO.
This register has the same bit fields and definitions as ADCSSFSTAT0 (see page 221) but is for
FIFO 2.
RO
0
ADC Sample Sequence Control 2 (ADCSSCTL2)
Offset 0x084
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
R/W
0
Reset
Type
000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TS3 IE3
END3 D3 TS2 IE2
END2 D2
TS1 IE1
END1 D1
TS0 IE0
END0 D0
reserved