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LM3S610-IQN50

LM3S610-IQN50首页预览图
型号: LM3S610-IQN50
PDF文件:
  • LM3S610-IQN50 PDF文件
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功能描述: Microcontroller
PDF文件大小: 2341.71 Kbytes
PDF页数: 共396页
制造商: ETC2[List of Unclassifed Manufacturers]
制造商LOGO: ETC2[List of Unclassifed Manufacturers] LOGO
制造商网址:
捡单宝LM3S610-IQN50
PDF页面索引
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120%
Analog-to-Digital Converter (ADC)
214 October 8, 2006
Preliminary
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028
This register provides a mechanism for application software to initiate sampling in the Sample
Sequencers. Sample sequences can be initiated individually or in any combination. When multiple
sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution
order.
Bit/Field Name Type Reset Description
31:4 reserved WO - Only a write by software is valid; a read of the register
returns no meaningful data.
3 SS3 WO - Only a write by software is valid; a read of the register
returns no meaningful d at a. When set by sof tware, sampling
is triggered on Sample Sequencer 3, assuming the
Sequencer is enabled in the ADCACTSS register.
2 SS2 WO - Only a write by software is valid; a read of the register
returns no meaningful d at a. When set by sof tware, sampling
is triggered on Sample Sequencer 2, assuming the
Sequencer is enabled in the ADCACTSS register.
1 SS1 WO - Only a write by software is valid; a read of the register
returns no meaningful d at a. When set by sof tware, sampling
is triggered on Sample Sequencer 1, assuming the
Sequencer is enabled in the ADCACTSS register.
0 SS0 WO - Only a write by software is valid; a read of the register
returns no meaningful d at a. When set by sof tware, sampling
is triggered on Sample Sequencer 0, assuming the
Sequencer is enabled in the ADCACTSS register.
reserved
WO
-
ADC Processor Sample Sequence Initiate (ADCPSSI)
Offset 0x028
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
WO
-
Reset
Type
---------------
WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO
reserved
SS0
SS1
SS2SS3
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