LM3S610 Data Sheet
October 8, 2006 213
Preliminary
Register 8 : ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020
This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has
the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence
priorities, each sequence must have a unique priority or the ADC behavior is inconsistent.
Bit/Field Name Type Reset Description
31:14 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
13:12 SS3 R/W 0x3 The SS3 field cont ain s a binary -enco ded value th at spec ifies
the priority encoding of Sample Sequencer 3. A priority
encoding of 0 is highest and 3 is lowest. The priorities
assign ed to the Sequenc ers must be uniqu ely mappe d. ADC
behavior is not consistent if two or more fields are equal.
11:10 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
9:8 SS2 R/W 0x2 The SS2 field c onta ins a bi nary-en co ded val ue that sp ecifie s
the priority encoding of Sample Sequencer 2.
7:6 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
5:4 SS1 R/W 0x1 The SS1 field c onta ins a bi nary-en co ded val ue that sp ecifie s
the priority encoding of Sample Sequencer 1.
3:2 reserved RO 0 Reserved bits return an indeterminate value, and should
never be changed.
1:0 SS0 R/W 0x0 The SS0 field c onta ins a bi nary-en co ded val ue that sp ecifie s
the priority encoding of Sample Sequencer 0.
reserved
reservedreserved
reserved
RO
0
ADC Sample Sequencer Priority (ADCSSPRI)
Offset 0x020
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset
Type
000000000000000
RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO
RO
0
Reset
Type
011001000010000
RO R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W R/W
reserved
SS0SS1SS2SS3